1. Field of the Invention
The present invention relates generally to a digital circuit, more particularly to a multiplexer circuit in which high speed operation and high integration can be achieved.
As is well known, the multiplexer is a device which selects and outputs any one of n input data in response to the control signal, and the technology has been developed for its high speed operation and high integration.
2. Description of Prior Art
FIG. 1 shows conventional multiplexer circuit of n to 1. The multiplexer circuit comprises n inverters I.sub.0 to I.sub.n-1 which are connected to n inputs b.sub.0 to b.sub.n-1 ; n pass transistors T.sub.0 to T.sub.n-1 which have n inverter outputs as inputs at their one ends, have selection signals a.sub.0 to a.sub.n-1 at their gates and have common node at their other ends; and a inverter 10 which is connected to the common node at the other ends of the pass transistor and outputs the inverted signals of selected final data.
If an arbitrary input signal b.sub.j (0.ltoreq.j.ltoreq.n-1) is selected by the selection signal induced at the gates of each pass transistor, the input signal is inverted at the inverter I.sub.j and passes to the pass transistor. Then, the input signal passes the common node a and is inverted at the inverter 10. The final output signal is the signal inverted at the inverter 10.
In the conventional multiplexer circuit described above, as the number of the bit of input data increases, the parasitic capacitance caused at the common node becomes large. The parasitic capacitance is generated additionally in the semiconductor device and does not exist in the circuit actually. Because of the large capacitance at the other ends of pass transistor, the delay time between input stage and output stage becomes long. Also, since all of n input stages has their inverters, the total size of circuit becomes large.